It starts executing at an address provided by the CPU when a bit in the video configuraion register is set. The video coprocessor provides instructions for video input, output, CPU interrupts, and DRAM refresh. If this coprocessor is not used to generate video it will normally be programmed to provided refresh signals for the DRAM chips connected to F21. The video coprocessor is started at an address that contains a programmed image, or possibly just refresh code. Using analog RGB outputs (sync on green), the image can have any size and shape within speed and memory bandwidth limitations. The pixel clock can run up to 20 MHz, with a corresponding frame rate. The image is formatted with vertical retrace lines, and scan lines with embedded horizontal retrace and blanking. These lines are contructed from Pixel, Sync and Jump instructions and probably include Refresh and Interrupt.
Using NTSC output the image has 525 lines of 115 words (60,334 words). It starts with a 21-line vertical-retrace for field-1 (VR1), the 241 even scan lines, a 22-line VR2 and the 241 odd scan lines. In memory, the VR1 is followed by VR2 and then 482 scan lines. Jump instructions thread these lines into the required order. If multiple images are in memory, they can share VR1 and VR2. Skip and Color-burst instructions are added for timing and synchronization. Blank is not distinguished from Black.
A 3-bit read/write register controls the processor: bit 19 . . . 15 . . . .10 . . . . 5 . . . . 0 - R T - - - - - - - - - 1 0 0 0 - A - - with R - 0 stop 1 run T - 0 pixel clock is CLK/2 1 pixel clock is CLK A - 0 continue at curent address 1 start at next Stack Processor addressThe pattern in bits 4-7 is required to start the processor in slot 0. There is no interrupt-enable. Including the Interrupt instruction in the image will generate an interrupt when it is executed.
Four 5-bit instructions are packed in each word. Instruction bits are patterns! Some instructions may occur only in certain slots.
bit 20 . . . . 15 . . . .10 . . . . 5 . . . . 0 slot 0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 Jump 1 0 a a a a a a a a a a a a a a a a a a address p p p a a a a a a a a a a a a a a a a a aThe Jump has an 18-bit address field. Address bits 20-18 are set by the Stack processor when it starts the Video processor (C2 set). The image is restricted to that quarter of DRAM. It may not cross this page boundary. Jump addresses must be -ored with 25555.
An NTSC image has been programmed so far in a resolution of 384x482 pixels. Pixels occupy 96 words of Horizontal-retrace (HR) uses 18 words and a Jump one more. NTSC images in this format have a 4x3 aspect, so pixels are not square. The large characters used by OK are 16x26 and provide 18 lines of 24 square characters.
code binary name slot cycles (140 ns at 7.16 Mhz clock) P 0 ---- Pixel - 1 0-F B 0 0000 Black/Blank - 1 0 S 1 0111 Sync - 1 17 R 1 1111 Refresh 2 0 1F J 1 1000 Jump 0 0 18 I Interrupt - 1 K 1 0011 Skip 0 -1 13 C 1 0101 Color-burst - 1 15 HR is coded: B B B B B B B B B S R S S S R S S S R S S S R S S S S S S S S S S S S S S S S S K S S S B B B C C C C C C C C C C C C C C C C B B B B B B B B B A scan line is coded: HR 96*(P P P P) JThe Jump skips over the next line (for interlace) or to a VR and takes no time. The Skip in slot 0 skips the Sync in slot 1, to provide 455 cycles at 7.16 Mhz per line.
VR1 is coded: E E E V V V E E E H H H H H H H H H H H H J VR2 is coded: H1 E E E V V V E E E H2 H H H H H H H H H H H H J with: H HR 96*(B B B B) - blank line H1 HR 39*(B B B B) H2 57*(B B B B) E B B B B B B B B B S R S S S R S S S S S S S S S S S B B 50*(B B B B) B B B B B B B B B S R S S S R S K S S S S S S S S S B B 50*(B B B B) V B B B B B B B B B S R S S S R S S S S S 48*(S S S S) B B B B B B B B B B B B B B B B B B B B B B B B B S R S S S R S K S S S 48*(S S S S) B B B B B B B B B B B B B B B BJump can be used within the pixel field to provide windowing. It takes a word of space, but no time. To assure timing, a Jump must not jump to another Jump or Refresh. The color modulation signal is generated from the 14MHz input as a square wave. It needs low-pass filtering, which can be done by a 100pF load capacitor:
Vi goes to a clock detect circuit that drives the crystal output during color burst, when the clock will be present. This requires that video input and output be synchronized within a clock cycle. This is done with software by examining the Vi clock in the I/O Port (P8), where color-burst can be identified.
Vi also goes to an analog multiplexer that connects it to Vo when a transparent pixel is encountered. There is no gain control on-chip, so an op-amp may be required to adjust signal level and amplitude.
Benson, K.B. TELEVISION ENGINEERING HANDBOOK, McGraw-Hill, 1986, ISBN 0-07-004779-0.