The F21c will have on chip ROM. The contents of this rom will be some test routines. These will include some block move, fill, and multiply routines. This experimental ROM has not yet been tested on any other chips. In F21c the code will be located near the control registers in the register space. This will add an overhead to jumps or calls into this code that will slightly offset the faster memory access to ROM. The ROM will have an 8ns setup time and a 4ns read time for a total access of 12ns. For linear stack oriented code this will be 4 instructions per 12ns or 3ns per instruction for 333mips.
The next version of F21 will move the ROM address space to a new location and possibly change the code stored in ROM.
The present ROM has four high frequency words in a DTC Forth implementation as well as block move, fill, and multiply code tables. The instructions in these tables are mapped into multiple ROM locations so that the same code appears to be repeated many times in ROM so that one can index into these code tables and use them as an unrolled inner loop in a block move, fill, or multiply routine.